ASPS-P15: Quantum, Accelerators, Processing-in-Memory Signal Processing
Poster
Fri, 8 May, 09:00 - 11:00
Location: Poster Area 32
Session Type: Poster
Track: Applied Signal Processing Systems [AS]
Click the to view the manuscript on IEEE Xplore Open Preview

ASPS-P15.1: A UNITARY QUANTUM PROCESS TOMOGRAPHY METHOD BASED ON A DENSITY MATRIX DIAGONALIZATION

Yannick Deville, University of Toulouse, France; Alain Deville, Aix-Marseille Université, France

ASPS-P15.2: FEDCOMPASS: FEDERATED CLUSTERED AND PERIODIC AGGREGATION FRAMEWORK FOR HYBRID CLASSICAL-QUANTUM MODELS

Yueheng Wang, Jiangnan University, China; Xing He, Zinuo Cai, Shanghai Jiao Tong University, China; Rui Zhang, Jiangnan University, China; Ruhui Ma, Shanghai Jiao Tong University, China; Yuan Liu, Jiangnan University, China; Rajkumar Buyya, University of Melbourne, Australia

ASPS-P15.3: Enhancing QAOA Ansatz via Multi-Parameterized Layer and Blockwise Optimization

Francesca De Falco, Leonardo Lavagna, Andrea Ceschini, Antonello Rosato, Massimo Panella, University of Rome La Sapienza, Italy

ASPS-P15.4: REAL-TIME CARFAC COCHLEA MODEL ACCELERATION ON FPGA FOR UNDERWATER ACOUSTIC SENSING SYSTEMS

Bram Bremer, Western Sydney University, Sydney, Australia, Australia; Matthew Bigelow, Stuart Anstee, Department of Defence, Australia; Gregory Cohen, Western Sydney University, Sydney, Australia, Australia; Andre van Schaik, Ying Xu, Western Sydney University, Australia

ASPS-P15.5: A UNIFIED HARDWARE ACCELERATOR FOR PRIVACY PRESERVING LLMS CLIENT-SIDE BASED ON CKKS HOMOMORPHIC ENCRYPTION

peiyang lin, jianwen liao, wei liu, yikang hao, ruicong tan, xiaoming xiong, shuting cai, Guangdong University of Technology, China

ASPS-P15.6: SIMULATORCODER: DNN ACCELERATOR SIMULATOR CODE GENERATION AND OPTIMIZATION VIA LARGE LANGUAGE MODELS

Yuhuan Xia, Tun Li, Hongji Zou, Xianfa Zhou, Chong Chen, Ruiyu Zhang, National University of Defense Technology, China

ASPS-P15.7: A Conflict-Free SpDMM Accelerator for GCN Inference on FPGA

Feng Yan, JunChen Liu, Oliver Sinnen, University of Auckland, New Zealand

ASPS-P15.8: A Queueing Model for Memory Controller Scheduler Subject to DRAM Column Access Timing Constraints

Navid Lashkarian, Matt Prather, Randall Rooney, Sujeet Ayyapureddi, Frank Ross, Micron, United States of America

ASPS-P15.9: MINIMIZING ADC PRECISION FOR ANALOG IN-MEMORY COMPUTING

Mihir Kavishwar, Naresh Shanbhag, University of Illinois at Urbana-Champaign, United States of America