Note: All times are in Pacific Daylight Time (UTC -7)
G-3: VLSI for 5G/B5G Communications Systems (invited) |
Session Type: Virtual |
Time: Tuesday, November 1, 08:00 - 09:00 |
Location: Virtual G |
Virtual Session: Attend on Virtual Platform |
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G-3.1: An Efficient Soft Output MIMO Detector Architecture Considering High-order Modulations |
Yai-Xin Dai; National Tsing Hua University |
SHIH-JIE JHANG; National Tsing Hua University |
Yen-Ming Chen; National Sun Yat-sen University |
Sheng-Ping Lan; National Tsing Hua University |
Yeong-Luh Ueng; National Tsing Hua University |
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G-3.2: A High-Throughput LDPC Decoder Architecture for Satellite Communication |
Suwen Song; Nanjing University |
Zhongfeng Wang; Nanjing University |
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G-3.3: List Ordered Statistics Decoders for Polar Codes |
Zongyao Li; Southeast University |
Leyu Zhang; Southeast University |
Yifei Shen; Southeast University |
Andreas Burg; Ecole Polytechnique Federale de Lausanne (EPFL) |
Xiaohu You; Southeast University |
Chuan Zhang; Southeast University |
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G-3.4: Hardware Efficient Radix-3/4/11 based FFT Processor for 5G NR Application |
Yakun Zhou; University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, High-tech Zone (Western District), Chengdu |
Chunping Yang; University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, High-tech Zone (Western District), Chengdu |
Jinsheng Kuang; University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, High-tech Zone (Western District), Chengdu |
Shaoxia He; University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, High-tech Zone (Western District), Chengdu |
Jienan Chen; University of Electronic Science and Technology of China, No. 2006, Xiyuan Avenue, High-tech Zone (Western District), Chengdu |
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