SS-SPS-2.4

An IDE for Reconfigurable Video Array Processor

Rong YANG, Xiaoyan XIE, Miaomiao CHAI, Lin FANG, Wanqi HE, Jingtao SUN, Xi'an University of Posts and Telecommunications, China
Session:
Reconfigurable Computing and Performance Evaluation
Track:
Signal Processing Systems: Design and Implementation (SPS)
Session Time:
Thu, 16 Dec, 09:00 - 11:00 Japan Standard Time (UTC +9)
Thu, 16 Dec, 00:00 - 02:00 Coordinated Universal Time
Wed, 15 Dec, 19:00 - 21:00 Eastern Standard Time (UTC -5)
Wed, 15 Dec, 16:00 - 18:00 Pacific Standard Time (UTC -8)
Session Chair:
Junyong Deng, Xi'an University of Posts & Telecommunications
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Session SS-SPS-2
TH1.LS-D.1: Improved Fruit Fly Optimization Algorithm Based on Simulated Annealing in Neural Network
Jin Wu, Wei Dai, Yu Wang, Bo Zhao, Xi’an University of Posts and Telecommunications, China
TH1.LS-D.2: An Implementation Method of HEVC Dataflow Graph Based on Reconfigurable Processer
Yun Zhu, Chuanzhan Hu, Xi’an University of Posts and Telecommunications, China; Lin Jiang, Xi’an University of Science and Technology, China; Xubang Shen, Xi'an Microelectronic Technology Research Institute, China
TH1.LS-D.3: AN IMPROVED NAIVE BAYES MODEL FOR AIR TEMPERATURE PREDICTION
BINGHONG JIANG, Xi’an Jiaotong University, China
TH1.LS-D.4: An IDE for Reconfigurable Video Array Processor
Rong YANG, Xiaoyan XIE, Miaomiao CHAI, Lin FANG, Wanqi HE, Jingtao SUN, Xi'an University of Posts and Telecommunications, China
TH1.LS-D.5: A Reconfigurable Parallelization of Generative Adversarial Networks based on Array Processor
Xiaoyan Xie, Miaomiao Chai, Zhuolin Du, Kun Yang, Shaorun Yin, Xi'an University of Posts and Telecommunications, China
TH1.LS-D.6: PERFORMANCE CHARACTERIZATION OF RASTERIZATION ALGORITHMS FOR RECONFIGURABLE GRAPHICS PROCESSOR
Junyong Deng, Qingqing Ma, Zekun Ye, Xi'an University of Posts and Telecommunications, China