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My ICASSP 2019 Schedule

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DISPS-L2: Algorithm and Architecture Co-optimization

Session Type: Lecture
Time: Tuesday, May 14, 17:30 - 19:30
Location: Syndicate 4
Session Chairs: Chao-Tsung Huang, National Tsing Hua University and Yeong-Luh Ueng, National Tsing Hua University
 
  DISPS-L2.1: LOW-COMPLEXITY RECURRENT NEURAL NETWORK-BASED POLAR DECODER WITH WEIGHT QUANTIZATION MECHANISM
         Chieh-Fang Teng; National Taiwan University
         Chen-Hsi (Derek) Wu; National Taiwan University
         Andrew Kuan-Shiuan Ho; National Taiwan University
         An-Yeu (Andy) Wu; National Taiwan University
 
  DISPS-L2.2: HARDWARE-FRIENDLY LDPC DECODING SCHEDULING FOR 5G HARQ APPLICATIONS
         Cing-Yi Liang; National Tsing Hua University
         Mao-Ruei Li; National Tsing Hua University
         Huang-Chang Lee; Chang Gung University
         Hsin-Yu Lee; National Tsing Hua University
         Yeong-Luh Ueng; National Tsing Hua University
 
  DISPS-L2.3: LOW-POWER PROGRAMMABLE PROCESSOR FOR FAST FOURIER TRANSFORM BASED ON TRANSPORT TRIGGERED ARCHITECTURE
         Jakub Žádník; Tampere University
         Jarmo Takala; Tampere University
 
  DISPS-L2.4: SYSTEM AND VLSI IMPLEMENTATION OF PHASE-BASED VIEW SYNTHESIS
         Han-Chih Huang; National Tsing Hua University
         Yu-Chih Wang; National Tsing Hua University
         Wei-Chih Chen; National Tsing Hua University
         Ping-Yen Lin; National Tsing Hua University
         Chao-Tsung Huang; National Tsing Hua University
 
  DISPS-L2.5: AN ITERATIVE TIME DOMAIN DENOISING METHOD
         Peter Tay; Western Carolina University
 
  DISPS-L2.6: HARDWARE-ORIENTED MEMORY-LIMITED ONLINE FASTICA ALGORITHM AND HARDWARE ARCHITECTURE FOR SIGNAL SEPARATION
         Lan-Da Van; National Chiao Tung University
         Tsung-Che Lu; National Chiao Tung University
         Tzyy-Ping Jung; University of California, San Diego
         Jo-Fu Wang; National Chiao Tung University