G-2: Improving the Efficiency of Neural Network Hardware: Devices, Circuits, Algorithms and Applications (invited) |
| Session Type: Virtual |
| Time: Monday, October 31, 09:30 - 10:30 |
| Location: Virtual G |
| Virtual Session: Attend on Virtual Platform |
| G-2.1: On Building Efficient and Robust Neural Network Designs |
| Xiaoxuan Yang; Duke University |
| Huanrui Yang; Duke University |
| Jingchi Zhang; Duke University |
| Hai Li; Duke University |
| Yiran Chen; Duke University |
| G-2.2: FPGA-based DNN Hardware Accelerator for Sensor Network Aggregation Node |
| Nadya Mohamed; Rice University |
| Joseph Cavallaro; Rice University |
| G-2.3: Efficient Multi-task Adaption for Crossbar-based In-Memory Computing |
| Fan Zhang; Arizona State University |
| Li Yang; Arizona State University |
| Deliang Fan; Arizona State University |
| G-2.4: VLSI Hardware Architecture of Neural A* Path Planner |
| Lingyi Huang; Rutgers University |
| Xiao Zang; Rutgers University |
| Yu Gong; Rutgers University |
| Boyang Zhang; Rutgers University |
| Bo Yuan; Rutgers University |