Note: All times are in Pacific Daylight Time (UTC -7)
| Paper: | G-2.2 |
| Paper Title: |
FPGA-based DNN Hardware Accelerator for Sensor Network Aggregation Node |
| Authors: |
Nadya Mohamed, Joseph Cavallaro, Rice University, United States |
| Session: | Improving the Efficiency of Neural Network Hardware: Devices, Circuits, Algorithms and Applications (invited) |
| Location: | Virtual G |
| Presentation Time: | Monday, October 31, 09:30 - 10:30 |
| Virtual Presentation: |
Attend on Virtual Platform |
| Presentation: |
Virtual
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| Topic: |
Architectures and Implementation: Invited Session: Improving the Efficiency of Neural Network Hardware: Devices, Circuits, Algorithms and Applications |