| Paper: | F2.2 | ||
| Paper Title: | FPGA-based DNN Hardware Accelerator for Sensor Network Aggregation Node | ||
| Authors: | Nadya Mohamed, Joseph Cavallaro, Rice University, United States | ||
| Session: | In-Person Posters IV | ||
| Location: | Fred Farr | ||
| Presentation Time: | Monday, October 31, 15:30 - 17:00 | ||
| Virtual Presentation: | Attend on Virtual Platform | ||
| Presentation: | Poster | ||
| Topic: | Architectures and Implementation: Invited Session: Improving the Efficiency of Neural Network Hardware: Devices, Circuits, Algorithms and Applications | ||