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My ICASSP 2020 Schedule

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Paper Detail

Paper IDWE2.I.4
Paper Title TIME-PREDICTABLE SOFTWARE-DEFINED ARCHITECTURE WITH SDF-BASED COMPILER FLOW FOR 5G BASEBAND PROCESSING
Authors Vanchinathan Venkataramani, Bruno Bodin, Aditi Kulkarni, Tulika Mitra, Li-Shiuan Peh, National University of SIngapore, Singapore
SessionWE2.I: Array-based Architectures for Energy-efficient Signal Processing Systems
LocationOn-Demand
Session Time:Wednesday, 06 May, 11:30 - 13:30
Presentation Time:Wednesday, 06 May, 12:30 - 12:50
Presentation Lecture
Topic Design and Implementation of Signal Processing Systems: [DIS-PROG] Programmable Hardware (FPGA, SoC, ASIC and others) for DSP algorithms
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