| Paper ID | DIS-L1.5 |
| Paper Title |
ACCELERATING LINEAR ALGEBRA KERNELS ON A MASSIVELY PARALLEL RECONFIGURABLE ARCHITECTURE |
| Authors |
Anuraag Soorishetty, Jian Zhou, Arizona State University, United States; Subhankar Pal, David Blaauw, Hun-Seok Kim, Trevor Mudge, Ronald Dreslinski, University of Michigan, United States; Chaitali Chakrabarti, Arizona State University, United States |
| Session | DIS-L1: Array-based Architectures for Energy-efficient Signal Processing Systems |
| Location | On-Demand |
| Session Time: | Wednesday, 06 May, 11:30 - 13:30 |
| Presentation Time: | Wednesday, 06 May, 12:50 - 13:10 |
| Presentation |
Lecture
|
| Topic |
Design and Implementation of Signal Processing Systems: [DIS-MLTC] Signal processing on multicore processors |
| IEEE Xplore Open Preview |
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| Virtual Presentation |
Click here to watch in the Virtual Conference |