| Paper ID | DIS-P2.8 |
| Paper Title |
LIGHTWEIGHT HARDWARE IMPLEMENTATION OF VVC TRANSFORM BLOCK FOR ASIC DECODER |
| Authors |
Ibrahim Farhat, VITEC, France; Wassim Hamidouche, INSA Rennes, France; Adrien Grill, VITEC, France; Daniel Menard, INSA Rennes, France; Olivier Déforges, Institut d'Electronique et de Télécommunications de Rennes / Institut Nationnal des Sciences Appliquées, France |
| Session | DIS-P2: Algorithm and Architecture Co-optimization |
| Location | On-Demand |
| Session Time: | Thursday, 07 May, 16:30 - 18:30 |
| Presentation Time: | Thursday, 07 May, 16:30 - 18:30 |
| Presentation |
Poster
|
| Topic |
Design and Implementation of Signal Processing Systems: [DIS-PROG] Programmable Hardware (FPGA, SoC, ASIC and others) for DSP algorithms |
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| Virtual Presentation |
Click here to watch in the Virtual Conference |