WA7b.2

A RISC-V Hardware Accelerator for AW-SOM Machine Learning

Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Tor Vergata University of Rome, Italy; Mariano Neroni, Simone Pace, MBDA Italia S.p.A., Italy; Sergio Spanò, Tor Vergata University of Rome, Italy
Session:
WA7b: Machine Learning Hardware Lecture
Track:
Architectures and Implementation
Location:
Oak Shelter
Presentation Time:
Wed, 30 Oct, 10:40 - 11:05 PT (UTC -8)
Session Chair:
François Leduc-Primeau, Polytechnique Montreal
Presentation
Discussion
Resources
No resources available.
Session WA7b
WA7b.1: Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU
Sasindu Wijeratne, University of Southern California, United States; Rajgopal Kannan, DEVCOM Army Research Lab, United States; Viktor Prasanna, University of Southern California, United States
WA7b.2: A RISC-V Hardware Accelerator for AW-SOM Machine Learning
Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Tor Vergata University of Rome, Italy; Mariano Neroni, Simone Pace, MBDA Italia S.p.A., Italy; Sergio Spanò, Tor Vergata University of Rome, Italy
WA7b.3: Hybrid SORN Support Vector Machine Classifier: A Hardware Implementation of the RBF Kernel
Nils Hülsmeier, Moritz Bärthel, University of Bremen, Germany; Jochen Rust, Hamburg University of Applied Sciences, Germany; Steffen Paul, University of Bremen, Germany
Contacts