A-2-3: Reconfigurable Computing and Performance Evaluation |
All times are in New Zealand Time (UTC +13) |
| Presentation Time: Wednesday, December 9, 17:15 - 19:15 Check your Time Zone |
| A-2-3.5: A PARALLELIZATION METHOD OF INCEPTION ARCHITECTURE BASED ON ARRAY PROCESSOR |
| Xiaoyan Xie; Xi’an University of Posts and Telecommunications |
| Zhuolin Du; Xi’an University of Posts and Telecommunications |
| Chuanzhan Hu; Xi’an University of Posts and Telecommunications |
| Kun Yang; Xi’an University of Posts and Telecommunications |
| Anqi Wang; Xi’an University of Posts and Telecommunications |
| A-2-3.6: RSP-BT:AN ADVANCED PARALLEL METHOD FOR DEPTH MAP MOTION ESTIMATION |
| Xiaoyan Xie; Xi'an University of Posts and Telecommunications |
| Anqi Wang; Xi'an University of Posts and Telecommunications |
| Yun Zhu; Xi'an University of Posts and Telecommunications |
| Chuanzhan Hu; Xi'an University of Posts and Telecommunications |
| Zhuolin Du; Xi'an University of Posts and Telecommunications |
| A-2-3.7: FAST INTER-FRAME PREDICTION BASED ARRAY PROCESSOR FOR DEPTH MAPS IN 3D-HEVC |
| Yun Zhu; Xi’an University of Posts and Telecommunications |
| Lin Jiang; Xi’an University of Science and Technology |
| Hui Song; Xi’an University of Posts and Telecommunications |
| Xiaoyan Xie; Xi’an University of Posts and Telecommunications |
| Anqi Wang; Xi’an University of Posts and Telecommunications |
| Xubang Shen; Xi'an Microelectronic Technology Research Institute |
| A-2-3.8: OPTIMIZATION OF FALSE-OVERLAP DETECTION OF TILE ASSEMBLY IN TILE-BASED RENDERING |
| Bowen Yang; Northwestern Polytechnical University |
| Meng Fan; Xi’an University of Posts and Telecommunications |
| Mengqiao Han; Xi’an University of Posts and Telecommunications |
| Yurong Geng; Xi’an University of Posts and Telecommunications |