| Paper ID | A-2-3.8 |
| Paper Title |
Optimization of False-Overlap Detection of Tile Assembly in Tile-based Rendering |
| Authors |
Bowen Yang, Northwestern Polytechnical University, China; Meng Fan, Mengqiao Han, Yurong Geng, Xi’an University of Posts and Telecommunications, China |
| Session |
A-2-3: Reconfigurable Computing and Performance Evaluation |
| Time | Wednesday, 09 December, 17:15 - 19:15 |
| Presentation Time: | Wednesday, 09 December, 19:00 - 19:15 Check your Time Zone |
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All times are in New Zealand Time (UTC +13) |
| Topic |
Signal Processing Systems: Design and Implementation (SPS): Special Session: Reconfigurable Computing and Performance Evaluation |
| Abstract |
With the rapid development of mobile devices, terminal devices put forward more requirements on GPU's real-time performance and power consumption. In this paper, tile-based architecture is adopted to improve the utilization of Mobile GPU resources on Mobile Graphics Processor (MGP).This architecture improves the rasterization execution rate through tile-binning generated tile list. However, before the execution of tile-binning, the overlap test will accumulate a large amount of computation when calculating the overlap relationship between primitives and triangles, even if a reasonable detection algorithm is adopted. In this paper, we propose a new method for segmentation of primitives, design an overlap detection algorithm with this method, and analyze the feasibility. Finally, the algorithm is mapped to the tile assembly platform using sort display algorithm, which aims to provide a concise tile list structure and an efficient overlap detection algorithm for mobile graphics processors. By using this algorithm, we can reduce memory overhead by 15% to 35%, CPU latency by 24% to 55%, and computing resources by 32% to 45%. |