| Paper ID | A-2-3.7 |
| Paper Title |
Fast Inter-frame Prediction Based Array Processor for Depth Maps in 3D-HEVC |
| Authors |
Yun Zhu, Xi’an University of Posts and Telecommunications, China; Lin Jiang, Xi’an University of Science and Technology, China; Hui Song, Xiaoyan Xie, Anqi Wang, Xi’an University of Posts and Telecommunications, China; Xubang Shen, Xi'an Microelectronic Technology Research Institute, China |
| Session |
A-2-3: Reconfigurable Computing and Performance Evaluation |
| Time | Wednesday, 09 December, 17:15 - 19:15 |
| Presentation Time: | Wednesday, 09 December, 18:45 - 19:00 Check your Time Zone |
|
All times are in New Zealand Time (UTC +13) |
| Topic |
Signal Processing Systems: Design and Implementation (SPS): Special Session: Reconfigurable Computing and Performance Evaluation |
| Abstract |
For the characteristics of the depth map with a large smooth area, it is not necessary in the 3D-High-Efficiency Video Coding (3D-HEVC) to use TZ search for inter-frame prediction. According to the parallelism of depth map inter-frame algorithms, analyzed the parallelism of full search, three-step search and diamond search in the array structure, this paper proposes a parallel implementation method of 3D-HEVC depth map inter-frame prediction based on array processor. Considering only the depth map encoding, the experimental results show that the synthesized frequency under the BEE4 FPGA chip is as high as 100.261MHZ. Compared with the software 3D-HEVC Test Model (HTM) version 16.1, without affecting the video quality, the speedup ratio of the full search mode can reach 35, the speedup ratio of the three-step search mode can reach 160, and the speedup ratio of the diamond search can reach 233. |