Deep learning is expected to greatly facilitate the operation of wireless receivers in challenging environments. However, traditional deep learning methods, when adapted to wireless receivers, struggle to adapt in real-time due to rapidly changing channels, hardware limitations, and latency constraints. In particular, conventional deep learning models, though powerful, are large, static, and ill-suited for dynamic, resource-limited environments, making real-time adaptation challenging. This demo proposal for ICASSP 2026 aims to showcase an innovative approach for realizing AI for wireless receivers that is both (i) lightweight and (ii) adaptive in orders of milliseconds. Our proposed solution leverages recent developments in modular, Bayesian architectures designed for rapid, online training and adaptation. In doing so, we develop autonomous, energy-efficient, and reliable physical-layer systems tailored for next-generation networks. Key to our approach is achieving real-time self-adaptation with training times in millisecond-order, with limited data and on hardware-constrained edge devices, by deviating from traditional stochastic gradient descent based optimization. Instead, we cast adaptation of AI receivers as ultra-fast lightweight continual Bayesian tracking to facilitate swift online learning and implement asynchronous training updates triggered only when drift detectors identify significant environmental changes. This strategy minimizes computational load while maintaining high responsiveness. The demo showcases our novel methodology using Pluto Plus SDR hardware to implement the receiver chain for OFDM Wi-Fi 802.11a/c signals. The standard equalizers and least squares symbol detection are replaced with an AI-aided pipeline comprised of a modular convolutional neural network constantly adapted using single-step Extended Kalman Filter (EKF) based continuous learning. Training data includes the 802.11 a/c synchronization symbols acquired from over-the-air signals and processed on GNU platform. Our demonstration highlights several key aspects of AI for wireless receivers: (i) it can lead to superior performance over classical equalizers; (ii) it can be made adaptive without inducing notable latency in neither inference nor learning; and importantly (iii) it can realize self-autonomous protocol-compliant wireless receivers on limited off-the-shelf SDR hardware. In doing so, we illustrate its potential for real-time, adaptive wireless communication systems.

Description: The demo consists of two nodes (UEs) transmitting video streams in the same time and frequency resources by mapping their messages onto end-to-end learned neural constellations optimized for over-the-air computation of their sum. A relay located between the UEs captures this composite signal, decodes the bitwise XOR sum of their messages, and retransmits the sum bits. Each UE receives the sum signal from the relay and subtracts its own message bits to recover the video stream from the other UE. Set-up: Two USRPs transmit the video streams of the two UEs and receive the sum of the streams from a third USRP functioning as the relay. The UEs and relay are controlled by MATLAB interfaces. Novelty and innovation: While traditional QAM constellations optimize the performance of individual transmitter-receiver links, coherent interference from another transmitting node can degrade its error performance. The neural constellations used by the UEs in this demo are optimized for over-the-air computation of the sum of their transmitted signals and offer better error rates when both the UEs are transmitting concurrently in the same frequency. The use of these neural constellations for signaling not only doubles the spectral efficiency, but it also reduces receiver complexity and decoding time at the relay node by circumventing the need to decode the individual messages through expensive successive interference cancellation or joint decoding operations. User interactivity 1. Live over-the-air communication using USRPs. 2. User interface for adjusting power and phase differences between the UEs (as a proxy for relative changes in UE locations). 3. Audience can also manipulate the antennas on the USRPs to see changes in the constellations received at the relay in real-time. 4. Live display of decoded video messages next to the original transmitted ones for comparison of video quality recovered through the neural scheme against the baseline (traditional QAM) scheme. 5. Display of the neural vs baseline constellations used at the UEs, and the respective sum constellations received at the relay in real-time. 6. Display of the live bit error rates.

Detailed description of the demo: In the journal paper: A. Agustin and X. Mestre, "Exploiting Multiple Polarizations in Extra Large Holographic MIMO," in IEEE Transactions on Wireless Communications, vol. 25, 2026, doi: 10.1109/TWC.2025.3623866 We investigated the spatial multiplexing capabilities of large multi-antenna configurations under line-of-sight and near field conditions with multiple orthogonal polarizations, by means of three infinitesimal dipoles. In the proposed demo we will show, on a small scale, when it is possible to use up to three spatial dimensions with tri-polarized antennas. Each prototyped tri-polarized antenna consists of a patch antenna (2 polarizations) and 1 monopole (perpendicular polarization) working at 2.45 GHz. Considering the transmitter and receiver are separated by around half-a meter (for the demo), it will be evaluated how the separation among the transmitter elements or the separation between transmitter and receiver influences the eigenvalues of the channel. The concept can be extended to larger distances if the aperture array increases. The demo is based on a single SDR with 8 radio frequency channels that controls the transmitted and received signals through the tri-polarized antenna (3 RF chains per antenna). The equivalent wireless channel is estimated from dedicated pilots sent by each transmitting polarization. Main novelty and innovations of the demo: This demo will present protypes of antennas with 3 polarizations and show under what conditions additional spatial streams can be transmitted in the near-field by means of polarized antennas. Impact to signal processing communities: Considering that conventional systems are designed to work with 2 polarizations, since communications are designed to work in the far field region, this demo shows a new dimension that can be exploited. Interactivity for attendees: The attendees will observe through the screen how the eigenvalues of the equivalent channel vary as a function of the distance of terminal and separation of transmitting antennas, elucidating the benefit of the near-field transmission.

This demo presents a flexible and low-cost Global Navigation Satellite System (GNSS) receiver prototype based on a System-on-Chip Field Programmable Gate Array (SoC FPGA) architecture, enabling efficient prototyping of experimental GNSS signals and advanced signal processing algorithms. The platform combines the adaptability of Software-Defined Radio (SDR) concepts with the massive parallelism and power efficiency of reconfigurable hardware, addressing the limited flexibility of Application-Specific Integrated Circuit (ASIC)-based receivers and the high power consumption of software-only implementations. The prototype integrates a Free and Open Source Software (FOSS) GNSS processing engine, providing full visibility and control over the baseband processing chain. The architecture emphasizes customization and reprogrammability, enabling researchers to implement, test, and refine novel receiver concepts. By offloading computationally intensive signal processing tasks to the FPGA while retaining software flexibility on the embedded processor, the proposed architecture achieves improved energy efficiency compared to software-only GNSS receivers operating on general-purpose processors. This balance between performance, power efficiency, and programmability enables advanced GNSS concepts to be evaluated in realistic field testing environments using small form factor (SFF) devices. The capabilities of the proposed platform have been validated through multiple concept implementations, including a low-power spaceborne GNSS receiver capable of processing signals in Low Earth Orbit scenarios, a real-time GNSS signal rebroadcaster enabling signal generation and regeneration with minimal latency, and a high-sensitivity GNSS receiver capable of acquiring and tracking weak signals with carrier-to-noise density ratios as low as 20 dB-Hz. Attendees will be guided through the configuration and operation of the receiver. A detailed description of the architecture will be provided, along with an explanation of how experimental signal processing strategies can be implemented within the GNSS processing engine. The demo will include a live demonstration, with the receiver operating in real time, and a post-processing demonstration using recorded multi-frequency and multi-constellation GPS and Galileo signals. The demonstrations will cover a static and a Low Earth Orbit (LEO) scenario, highlighting the platform’s capabilities under different signal conditions. During the demo, standard-format receiver outputs, such as navigation solutions and measurement data, will be demonstrated, and key receiver measurements will be monitored live to illustrate real-time system performance.

Quantum computing could transform fields like drug discovery, materials science, and cryptography. However, qubits are susceptible to noise, decoherence, and operational errors that rapidly corrupt information. Robust quantum error correction (QEC) is vital for scaling past today’s noisy prototypes. QEC must operate with micro-to-nanosecond-scale latency and high reliability to maintain logical error rates below 1e-12 to achieve fault tolerance. Low-density parity-check (LDPC) codes are classical error correction schemes defined by a binary parity-check (PC) matrix that can be represented as a Tanner graph. LDPC codes are decoded using graph-based iterative message passing, i.e., belief propagation (BP). Their QEC counterparts, quantum LDPC (QLDPC) codes, are defined by quaternary PC matrices to handle the three types of Pauli errors under the depolarizing quantum noise model. QLDPC codes can be decoded via quaternary BP4. In this demo, a custom hardware architecture of an FPGA-based QEC simulator will be demonstrated. We consider the [[126, 28]] and [[254, 28]]] generalized bicycle QLDPC codes. The core component is a fixed-point hardware-optimized BP4 decoder implemented in HDL. The decoder is specifically designed to efficiently decode QLDPC codes with low latency and low complexity. Our FPGA demo emulates a quantum (depolarizing) channel in real time, with channel quality (physical error rate) controllable by the attendees. The attendees will also be able to pick the QEC code and the parameters (e.g., number of iterations) of the BP decoder on the FPGA in runtime. Resulting logical error rates and the decoding latency (in nano or microsecond scale) will be visualized (vs. physical error rate) in Jupyter Notebook environment connected to the FPGA board. Our implementation (A) utilizes less than 25% of the resources on a commercially-available FPGA; (B) achieves a logical error rate of about 1e-12 at a physical error rate of 1e−4, with an average decoding latency below 50 nanoseconds; and (C) decodes 15.8 Mcodewords/s. (A) allows it to potentially coexist with the DSP and control algorithms required in quantum computers. (B) and (C) demonstrate to the broader quantum signal processing community the feasibility of integrating high-reliability low-latency QEC in future quantum systems.