WA6b.3

Single-stage 2-way fp4 Merge Sort Using Hardware Carry Chain Logic

Robert Kent, Marios Pattichis, University of New Mexico, United States
Session:
WA6b: Track G Session I Lecture
Track:
Architectures and Implementation
Location:
Room 6
Presentation Time:
Wed, 28 Oct, 11:05 - 11:30 PT (UTC -7)
Presentation
Discussion
Resources
No resources available.
Session WA6b
WA6b.1: Configurable SIMD Log-Floating Point Multiplier
Quentin Koeninger, Hridi Prova Debnath, James E. Stine, Shahriar Shahabuddin, Oklahoma State University, United States
WA6b.2: AFG: An Asymmetric Fast Givens Systolic Array with Unitary-Grade Stability in Fixed-Point Hardware
Carl Ingemarsson, Swedish Defence Research Agency (FOI), Sweden
WA6b.3: Single-stage 2-way fp4 Merge Sort Using Hardware Carry Chain Logic
Robert Kent, Marios Pattichis, University of New Mexico, United States
Contacts