TP6b5.5

Multiplier Optimization via E-Graph Rewriting

Andy Wanna, Imperial College London, United Kingdom; Samuel Coward, Imperial College London & Intel Corporation, United Kingdom; Theo Drane, Intel Corporation, United States; George Constantinides, Imperial College London, United Kingdom; Milos Ercegovac, University of California, Los Angeles, United States
Session:
TP6b5: Architectures and Algorithms I Poster
Track:
Architectures and Implementation
Location:
Fred Farr
Presentation Time:
Tue, 31 Oct, 15:30 - 17:35 PT (UTC -8)
Session Co-Chairs:
Anastasia Volkova, INRIA and Sebastian Roy, Université de Sherbrooke
Presentation
Discussion
Resources
No resources available.
Session TP6b5
TP6b5.1: Detection of Unknown-Unknowns in Human-in-Loop Human-in-Plant Systems Using Physics Guided Process Models
Aranyak Maity, Ayan Banerjee, Sandeep Gupta, Arizona State University, United States
TP6b5.2: A Vibrational Radar Backscatter Communication Experimental Testbed
Jessica Centers, Jeffrey Krolik, Duke University, United States
TP6b5.3: Non-Subtractive Dither for Squared Error Linearization of Lloyd-Max Quantizers
Morriel Kasher, Rutgers University, United States; Michael Tinston, Expedition Technology, Inc., United States; Predrag Spasojevic, Rutgers University, United States
TP6b5.4: Optimizing Dither Distributions for Noisy Quantization Systems
Morriel Kasher, Rutgers University, United States; Michael Tinston, Expedition Technology, Inc., United States; Predrag Spasojevic, Rutgers University, United States
TP6b5.5: Multiplier Optimization via E-Graph Rewriting
Andy Wanna, Imperial College London, United Kingdom; Samuel Coward, Imperial College London & Intel Corporation, United Kingdom; Theo Drane, Intel Corporation, United States; George Constantinides, Imperial College London, United Kingdom; Milos Ercegovac, University of California, Los Angeles, United States
TP6b5.6: Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures
Alex Underwood, James Stine, Oklahoma State University, United States
TP6b5.7: Signed-Digit Addition Based on CNFETs and Ternary Logic
Sébastien Roy, Université de Sherbrooke, Canada
TP6b5.8: Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Univ. of Rome Tor Vergata, Italy; Alberto Nannarelli, Technical University of Denmark, Denmark; Marco Re, Univ. of Rome Tor Vergata, Italy
TP6b5.9: Hardware Implementation of RF Spectral Convergence System on DASH SoC
Saquib Siddiqui, Arindam Dutta, Alex Chiriyath, Drake Silbernagel, Prithvi Hemanth, Owen Ma, Jacob Holtom, Nishita Luhana, Daniel Bliss, Arizona State University, United States
TP6b5.10: Design and Synthesis of RISC-V Bit Manipulation Extensions
Kevin Kim, David Harris, Kip Macsai-Goren, Harvey Mudd College, United States
TP6b5.11: Using Evolutionary Computation to Optimize Task Performance of Unclocked, Recurrent Boolean Circuits in FPGAs
Raphael Norman-Tenazas, David Kleinberg, Erik C. Johnson, Johns Hopkins University Applied Physics Laboratory, United States; Daniel P. Lathrop, Recurrent Computing, Inc., United States; Matthew J. Roos, Johns Hopkins University Applied Physics Laboratory, United States
TP6b5.12: Parallelization of the Shift and Add Reducer
Ryan Swann, James Stine, Oklahoma State University, United States
TP6b5.13: Hardware-Optimal Digital FIR Filters: One ILP to Rule Them All and in Faithfulness Bind Them
Anastasia Volkova, Inria, France; Rémi Garcia, Nantes Université, France; Florent de Dinechin, INSA Lyon, France; Martin Kumm, Fulda University of Applied Sciences, Germany
TP6b5.14: Unlocking the Potential of LDPC Decoders with PiM Acceleration
Oscar Ferraz, Instituto de Telecomunicacoes, University of Coimbra, Portugal; Yann Falevoz, UPMEM, France; Vitor Silva, Gabriel Falcao, Instituto de Telecomunicacoes, University of Coimbra, Portugal
Contacts