G-6: Hardware Accelerators |
| Session Type: Virtual |
| Time: Tuesday, November 02, 11:15 - 12:45 |
| Location: Room 6 |
| Virtual Session: Attend on Virtual Platform |
| Session Chair: James Stine, Oklahoma State University |
| G-6.1: VLSI Hardware Architecture of Stochastic Low-rank Tensor Decomposition |
| Lingyi Huang; Department of Electrical and Computer Engineering, Rutgers University |
| Chunhua Deng; Department of Electrical and Computer Engineering, Rutgers University |
| Shahana Ibrahim; School of Electrical Engineering and Computer Science, Oregon State University |
| Xiao Fu; School of Electrical Engineering and Computer Science, Oregon State University |
| Bo Yuan; Department of Electrical and Computer Engineering, Rutgers University |
| G-6.2: Time-Multiplexed Pilot-Hopping Sequence Detection Architecture for Massive Machine-Type Grant-Free Random Access |
| Vishal Bangalore Kumar Swamy; Linköping University |
| Mikael Henriksson; Linköping University |
| Narges Mohammadi Sarband; Linköping University |
| Oscar Gustafsson; Linköping University |
| G-6.3: A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware |
| Ryan Swann; Oklahoma State University |
| James Stine; Oklahoma State University |
| G-6.4: Instruction Extension of RV32I and GCC Back End for ASCON Lightweight Cryptography Algorithm |
| Özlem Altınay; İstanbul Technical University |
| Berna Örs; İstanbul Technical University |