Note: All times are in Pacific Daylight Time (UTC -7)
G-2: Architectures and Implementation |
| Session Type: Virtual |
| Time: Tuesday, November 02, 11:15 - 12:45 |
| Location: Room 6 |
| Virtual Session: Attend on Virtual Platform |
| Session Chair: Gabriel Falcao, University of Coimbra
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G-2.1: Inter-actions parallel execution on GPU from high-level dataflow synthesis |
| Aurelien Bloch; École Polytechnique Fédérale de Lausanne |
| Simone Casale-Brunet; École Polytechnique Fédérale de Lausanne |
| Marco Mattavelli; École Polytechnique Fédérale de Lausanne |
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G-2.2: Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs |
| Aman Arora; The University of Texas at Austin |
| Bagus Hanindhito; The University of Texas at Austin |
| Lizy K. John; The University of Texas at Austin |
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G-2.3: On the Performance of Link Space Communications using NB-LDPC Codes on Embedded Parallel Systems |
| Oscar Ferraz; Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal |
| Vitor Silva; Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal |
| Gabriel Falcao; Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal |
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G-2.4: Memory-Efficient SFDR-Optimized Post-Correction of Analog-to-Digital Converters via Frequency-Selective Look-Up Tables |
| Morriel Kasher; Rutgers University |
| Predrag Spasojevic; Rutgers University |
| Michael Tinston; Expedition Technology, Inc. |
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G-2.5: Profile-guided latency optimization for high-level synthesis of dataflow programs |
| Endri Bezati; EPFL |
| Mahyar Emami; EPFL |
| Jorn Janneck; Lund University |
| James Larus; EPFL |
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