Note: All times are in Pacific Daylight Time (UTC -7)
| Paper: | G-6.1 |
| Paper Title: |
VLSI Hardware Architecture of Stochastic Low-rank Tensor Decomposition |
| Authors: |
Lingyi Huang, Chunhua Deng, Bo Yuan, Department of Electrical and Computer Engineering, Rutgers University, United States; Shahana Ibrahim, Xiao Fu, School of Electrical Engineering and Computer Science, Oregon State University, United States |
| Session: | Hardware Accelerators |
| Location: | Room 6 |
| Presentation Time: | Tuesday, November 02, 11:15 - 12:45 |
| Virtual Presentation: |
Attend on Virtual Platform |
| Presentation: |
Virtual
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| Topic: |
Architectures and Implementation: Accelerators |