| Paper ID | A-2-3.3 |
| Paper Title |
An Evaluation of High-Throughput Scalable Radix-4 FFT Processor Architecture Using Fixed-Point Arithmetic |
| Authors |
Tomotaka Kawabata, Hiroshi Tsutsui, Hokkaido University, Japan |
| Session |
A-2-3: Design and Implementation for Advanced Wireless Communication Systems |
| Time | Wednesday, 09 December, 17:15 - 19:15 |
| Presentation Time: | Wednesday, 09 December, 17:45 - 18:00 Check your Time Zone |
|
All times are in New Zealand Time (UTC +13) |
| Topic |
Signal Processing Systems: Design and Implementation (SPS): Special Session: Design and Implementation for Advanced Wireless Communication Systems |
| Abstract |
In this paper, we propose a scalable and high-throughput pipeline FFT processor architecture and evaluate its variations. To achieve high-throughput with reasonable operating frequency, the proposed architecture utilizes radix-4, where four points are processed every clock cycle. Like IP core generators, our architecture can be reconfigured by changing the number of FFT stages to support various numbers of FFT points. Our architecture is based on fixed-point arithmetic to relieve the complexity but might be extended to support floating-point implementation to keep high dynamic ranges. The proposed architecture achieves four times the throughput of the operating frequency. For example, 492 M samples/sec of throughput can be achieved when the operating frequency is 123 MHz, which may be a reasonable performance for 5G OFDM implementation. In this case, the gate count of our 4K-point FFT is 443,419, excluding SRAMs for pipeline buffers. |