| Paper ID | A-1-3.2 |
| Paper Title |
A NEW ALGORITHM TO DERIVE HARDWARE EFFICIENT INTEGER DISCRETE COSINE TRANSFORM FOR HEVC |
| Authors |
Boyu Qin, Jiajia Chen, Nanjing University of Aeronautics and Astronautics, China |
| Session |
A-1-3: Signal Processing Systems for Communication and Multimedia |
| Time | Tuesday, 08 December, 17:15 - 19:15 |
| Presentation Time: | Tuesday, 08 December, 17:30 - 17:45 Check your Time Zone |
|
All times are in New Zealand Time (UTC +13) |
| Topic |
Signal Processing Systems: Design and Implementation (SPS): |
| Abstract |
HEVC (High Efficiency Video Coding) is a popular video coding standard. With the rapid development of multimedia technology, people pursue not only the high-definition of video, but also the portability and miniaturization of devices, which brings great challenges to the low-power design of video encoding chips. To provide solution to address both compression quality and hardware efficiency, a measure for evaluating the hardware cost in integer DCT unit of HEVC is proposed in this paper, which helps to determine the most hardware efficient transform matrix. In addition, Genetic Algorithm is used to solve the multi-objective optimization to derive the solution for better coding performance. Experiments show that the transform matrix derived and its hardware implementation has advantages in both hardware cost and coding performance. Compared with the most competitive methods in recent years, the hardware cost of the proposed method has been successfully reduced by at least 15.35% of chip area and 4.91% of power consumption. |